Integrated Circuit Design

Analog and Mixed Signal Design

Experienced in popular processes.

FinFET CMOS 22nm and 16nm designs
Planar CMOS logic processes: 0.13um, 90nm and 22nm
Planar CMOS analog processes: 0.35um and 0.18um

Analog Front Ends - Signal Path

Amplifiers (various): OTA, Rail-Rail, Class A/B
Anti-Aliasing Filters, Equalization / Boost
Analog-to-Digital Converters (ADC)

RFID / NFC

Ultra Low Power. Nano-ampere bias currents
Sub-threshold Design
Energy Harvesting / Passive Power
Rectification and Regulation
Back Scatter / Load Modulation

Clocking

PLL design: PFD, Loop Filters, Dividers, etc.
VCO - low phase noise
Crystal Oscillators
VCXO, OCXO
SERDES development
Impedance Calibration
Low Jitter techniques

Power & Misc

Linear Regulators
Power-On-Reset
Supply and startup sequencing multi-domains
Band-Gap Voltage References - precision
Temperature Sensors
Trim DAC's for precision calibration

Verification

Behavioral Modelling (Verilog AMS and similar)
LVS (Layout vs Schematic)
DRC (Design Rule Check)
ERC (Electrical Rule Check)
Extraction
Signal Integrity
Ansys Totem: EM, IR.
Logic Equivalency Check (LEC)